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log and resolve call sites
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parent
862159116c
commit
1997297d7b
3 changed files with 61 additions and 9 deletions
0
crates/vestal/src/call.rs
Normal file
0
crates/vestal/src/call.rs
Normal file
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@ -31,7 +31,7 @@ impl Vestal {
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let dep = descriptor.get_name(dll)?.as_str()?;
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let iat = descriptor.get_first_thunk(dll)?;
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let ilt = descriptor.get_original_first_thunk(dll)?;
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let lookups = descriptor.get_lookup_thunks(dll)?;
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let lut = descriptor.get_lookup_thunks(dll)?;
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let resolved = Arc::new(self.resolve(&dep)?.expect("no path for {name}"));
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print!(" (module {BOLD}{dep:?}{RESET} N=0x{:>08x} IAT=0x{:>08x} ILT=0x{:>08x}\n {resolved:?}",
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&descriptor.name.0,
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@ -47,7 +47,7 @@ impl Vestal {
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Thunk::Thunk32(t) => panic!("32 bit original thunk"),
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Thunk::Thunk64(t) => t.0
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})),
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lookups.iter().map(|thunk|format!("0x{:08x}", match thunk {
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lut.iter().map(|thunk|format!("0x{:08x}", match thunk {
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Thunk::Thunk32(t) => panic!("32 bit original thunk"),
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Thunk::Thunk64(t) => t.0
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})),
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@ -72,7 +72,7 @@ impl Dll {
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let text = &data[start..start+size];
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let mut calls_by_source = Default::default();
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let mut calls_by_target = Default::default();
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let _ = Self::calls(
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let calls = Self::calls(
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&name,
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&pe,
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start,
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@ -81,6 +81,7 @@ impl Dll {
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&mut calls_by_target,
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false
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)?;
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let imports = Self::imports(&pe);
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let dll = Arc::new(Self {
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name: name.clone(),
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path: path.clone(),
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@ -91,9 +92,66 @@ impl Dll {
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calls_by_source,
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calls_by_target,
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});
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println!(" (call-sites {calls})");
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for (call, sites) in dll.calls_by_target.iter() {
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println!(" (0x{call:08x}\n {:?})", sites.iter()
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.map(|call|format!("0x{:08x}", call.offset))
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.collect::<Vec<_>>());
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}
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build.dlls.insert(name.clone(), dll.clone());
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Ok(dll)
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}
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fn imports (pe: &VecPE) -> Usually<(usize, usize)> {
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let directory = ImportDirectory::parse(pe)?;
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for descriptor in directory.descriptors {
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let dep = descriptor.get_name(pe)?.as_str()?;
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let imp = descriptor.get_imports(pe)?;
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let iat = descriptor.get_first_thunk(pe)?;
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let ilt = descriptor.get_original_first_thunk(pe)?;
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let lut = descriptor.get_lookup_thunks(pe)?;
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let mut imports = Vec::new();
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for (index, (import, thunk, orig, lookup)) in izip!(
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imp,
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iat.iter().map(|thunk|format!("0x{:08x}", match thunk {
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Thunk::Thunk32(t) => panic!("32 bit thunk"),
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Thunk::Thunk64(t) => t.0
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})),
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ilt.iter().map(|thunk|format!("0x{:08x}", match thunk {
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Thunk::Thunk32(t) => panic!("32 bit original thunk"),
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Thunk::Thunk64(t) => t.0
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})),
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lut.iter().map(|thunk|format!("0x{:08x}", match thunk {
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Thunk::Thunk32(t) => panic!("32 bit original thunk"),
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Thunk::Thunk64(t) => t.0
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})),
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).enumerate() {
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let call_via = descriptor.first_thunk.0 + index as u32 * 8;
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let name = match import {
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ImportData::Ordinal(x) => {
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//print!("\n (import-ordinal {BOLD}0x{:>08x}{RESET} IAT={} ILT={} LU={} 0x{:>04x})",
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//call_via, thunk, orig, lookup, x);
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format!("___VESTAL___ORD___{x}___")
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},
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ImportData::ImportByName(name) => {
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//print!("\n (import-by-name {BOLD}0x{:>08x}{RESET} IAT={} ILT={} LU={} {:?})",
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//call_via, thunk, orig, lookup, name);
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format!("{name}")
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},
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};
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println!(" ({index:5} 0x{call_via:08x} {dep:>20} {name}");
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imports.push((thunk, orig, import));
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//if let Some(existing) = self.addr_to_import.get(&call_via) {
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//panic!("addr space overlap at 0x{call_via:x}: {}::{} vs {}::{}",
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//existing.0,
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//existing.1,
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//dep.to_string(),
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//name);
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//}
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//self.addr_to_import.insert(call_via, (dep.to_string(), name));
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}
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}
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Ok((0, 0))
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}
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fn calls (
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name: &Arc<str>,
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pe: &VecPE,
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@ -115,12 +173,6 @@ impl Dll {
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calls_by_target.get_mut(&call.target).unwrap().push(call);
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}
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}
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println!(" (call-sites {calls})");
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for (call, sites) in calls_by_target.iter() {
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println!(" (0x{call:08x}\n {:?})", sites.iter()
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.map(|call|format!("0x{:08x}", call.offset))
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.collect::<Vec<_>>());
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}
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Ok(calls)
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}
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fn call (
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