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wip: dsl, input, output, proc: more precise lifetimes
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🪞👃🪞 2025-05-09 18:17:10 +03:00
parent 22d63eed9c
commit 5e09f5a4bb
11 changed files with 140 additions and 122 deletions
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6
proc/src/proc_view.rs
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@ -55,8 +55,10 @@ impl ToTokens for ViewDef {
}
}
/// Generated by [tengri_proc].
impl<'a> ::tengri::output::ViewContext<'a, #output> for #ident {
fn get_content_sym (&'a self, value: &Value<'a>) -> Option<RenderBox<'a, #output>> {
impl<'state> ::tengri::output::ViewContext<'state, #output> for #ident {
fn get_content_sym <'source: 'state> (&'state self, value: &Value<'source>)
-> Option<RenderBox<'state, #output>>
{
match value {
#(#exposed)*
_ => panic!("expected Sym(content), got: {value:?}")