diff --git a/tek/src/view.rs b/tek/src/view.rs index 6f4ace2a..e7a5f986 100644 --- a/tek/src/view.rs +++ b/tek/src/view.rs @@ -1,19 +1,6 @@ use crate::*; pub(crate) use std::fmt::Write; pub(crate) use ::tek_tui::ratatui::prelude::Position; -/// Clear a pre-allocated buffer, then write into it. -#[macro_export] macro_rules! rewrite { - ($buf:ident, $($rest:tt)*) => { |$buf,_,_|{$buf.clear();write!($buf, $($rest)*)} } } -/// Define a type alias for iterators of sized items (columns). -macro_rules! def_sizes_iter { - ($Type:ident => $($Item:ty),+) => { - pub(crate) trait $Type<'a> = - Iterator + Send + Sync + 'a;}} -def_sizes_iter!(ScenesSizes => Scene); -def_sizes_iter!(TracksSizes => Track); -def_sizes_iter!(InputsSizes => JackMidiIn); -def_sizes_iter!(OutputsSizes => JackMidiOut); -def_sizes_iter!(PortsSizes => Arc, [PortConnect]); pub(crate) trait ScenesColors<'a> = Iterator>; pub(crate) type SceneWithColor<'a> = (usize, &'a Scene, usize, usize, Option); view!(TuiOut: |self: Tek| self.size.of(View(self, self.view)); { diff --git a/tek/src/view_memo.rs b/tek/src/view_memo.rs index 55a2ecf8..59e75b5d 100644 --- a/tek/src/view_memo.rs +++ b/tek/src/view_memo.rs @@ -1,4 +1,9 @@ use crate::*; + +/// Clear a pre-allocated buffer, then write into it. +#[macro_export] macro_rules! rewrite { + ($buf:ident, $($rest:tt)*) => { |$buf,_,_|{$buf.clear();write!($buf, $($rest)*)} } } + #[derive(Debug, Default)] pub(crate) struct ViewMemo { pub(crate) value: T, pub(crate) view: Arc> diff --git a/tek/src/view_sizes.rs b/tek/src/view_sizes.rs index 7bb2146e..c5278862 100644 --- a/tek/src/view_sizes.rs +++ b/tek/src/view_sizes.rs @@ -1,4 +1,17 @@ use crate::*; + +/// Define a type alias for iterators of sized items (columns). +macro_rules! def_sizes_iter { + ($Type:ident => $($Item:ty),+) => { + pub(crate) trait $Type<'a> = + Iterator + Send + Sync + 'a;}} + +def_sizes_iter!(ScenesSizes => Scene); +def_sizes_iter!(TracksSizes => Track); +def_sizes_iter!(InputsSizes => JackMidiIn); +def_sizes_iter!(OutputsSizes => JackMidiOut); +def_sizes_iter!(PortsSizes => Arc, [PortConnect]); + impl Tek { /// Spacing between tracks. pub(crate) const TRACK_SPACING: usize = 0;